BRIDGING THE GAP FOR HARDWARE TRANSACTIONAL MEMORY
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INTRODUCTION AND BACKGROUND
Mutex locks have long been used as a mechanism to provide atomicity in shared memory programs. A thread that accesses a shared object in memory is required to first acquire the mutex associated with that object. The lock allows only one thread at a time to hold it, thus ensuring atomicity for an operation on the shared object. To simplify programming, a lock typically protects more than one memory location. This can result in unnecessary serialization on the lock even when different threads perform operations on disjoint sets of memory locations, i.e. when the operations could have been performed concurrently yet atomically. Thus locks represent a pessimistic concurrency control mechanism. In contrast, transactional memory (TM) provides optimistic concurrency control. TM allows concurrent transactions to speculatively execute code that accesses shared memory. Transactions for which no conflict is detected are allowed to commit their work, avoiding unnecessary serialization. When a conflict is detected, e.g. when two concurrent transactions try to write to the same memory location, the conflict must be resolved, typically by delaying or aborting one of the conflicting transactions. Until recently, only software-based TM systems have been available to users, whereas hardware transactional memory (HTM) was only a (very active) research topic. This has changed with the introduction of several commercial HTM offerings [1, 2, 3]. However, while much HTM research has focused on sophisticated HTM proposals that provide strong guarantees and extensively change the coherence protocol (or completely replace it with TM-specific coherence [4]), the commercial offerings mostly use much simpler implementations, often dubbed “best-effort” for their lack of any guarantees that an HTM transaction will ever commit1 , and with a “requester-wins” approach to conflict resolution that does 1Exceptions to this exist, but place severe restrictions on the operations that can be placed in a transaction. 1 not require any changes to the underlying coherence protocol [5]. In these HTMs, data conflict detection relies on the coherence protocol. When a transaction needs to access a cache block, the block is requested using the unmodified coherence protocol. If this block is held by another core in a conflicting coherence state, that core gets an invalidation or downgrade request that forces it to change its coherence state. A transaction running on the core receiving such a request must be aborted. In other words, the “requester” transaction has “won” the conflict. However, such a policy can result in aborting transactions that have done more work instead of those that have done less work, and creates a strong bias against long running transactions that have already accessed many blocks. The long running transactions are “vulnerable” to aborts from many small- /young transactions that may access one of those blocks. Thus requester-wins HTMs can experience performance degradation when there are many data conflicts between transactions. The reason best-effort, requester-wins HTMs are popular in commercial offerings is that they are easier to implement. However, even supposedly simple HTM designs can be difficult to implement correctly [6]. This argues for focusing performance improvement efforts on this style of HTM, rather than on more complex HTMs that are less likely to be used in practice. Figure 1.1 shows a high-level depiction of our baseline architecture. The HTM Engine contains hardware that manages the transaction, such as the Abort Pending bit that signals whether the running transaction has been aborted, and the Abort Hardware that rolls back updates by the aborted transaction. In the private cache, each block has an additional Transactional (tnx) bit, which indicates whether the line has been accessed by the transaction (thus adding them to the read or write set). Coherence messages are sent through the Coherence Layer, which also contains the Directory. To request read or write permissions, cores send standard coherence protocol messages down to the Coherence Layer. When a coherence invalidate or downgrade mes2 sage for a cache block with its tnx bit set arrives, this means that there has been a data conflict on that address. This sets the Abort Pending bit, triggering the transaction abort. Private Cache Core 0 HTM Engine Abort Pending Tnx Tnx Abort Hardware Line 0 Line 1 Coherence Layer Private Cache Core 1 HTM Engine Abort Pending Tnx Tnx Abort Hardware Line 0 Line 1 Figure 1.1: Baseline HTM Architecture This type of best-effort HTM has been the dominant mechanism in providing TM support for commercial offerings [1, 7, 2, 3, 8]. The implementation is relatively low-cost and when there is little data contention, best-effort HTMs perform very well. Data conflict checking is done at access time, which means that there is little work required at commit time. More importantly, requester-wins HTMs leave the coherence protocol unchanged. There are no additional message types or coherence states that can complicate the coherence protocol and its verification. In other words, the coherence protocol is unaware of the HTM. However, with data conflicts, best-effort HTMs can have lower performance than more sophisticated HTMs. One problem is that requester-wins HTMs often penalize older transactions that have done more work instead of younger ones. When a transaction conflicts with another, older, transaction by requesting data already accessed by the older one, the core running the younger transaction is the requester, and the core with the older one is 3 the responder. The responder core has no option except to honor the request, aborting the older transaction. In other words, the older transaction “loses” against the younger one. However, this is often suboptimal because the older transaction has done more work than the younger one, and this makes it harder for large transactions to succeed in the presence of many small transactions.
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